The present invention relates to integrated circuit isolation technology.
In integrated circuit technology, it is always necessary to separate the active regions of active devices (the "moat regions") one from another. In LSI and VLSI integrated circuits using MOS technology, this is usually performed by LOCOS (an acronym for "local oxidation of silicon"). In LOCOS, a patterned nitride is used to cover the areas which will be the moat regions, and the field oxide is then grown, by exposure to a high-temperature oxidizing ambient, in the exposed regions. However, it has long been recognized as a problem with this technology that the field oxide will not only grow vertically in the exposed regions, but will also grow laterally underneath the edges of the nitride mask. The lateral oxide encroachment (known as "bird's-beak") under the nitride is about half the field-oxide thickness, and this means that substantial real estate is wasted in this isolation technology.
A newer isolation technology, which is generally known by the acronyms SWAMI (Sidewall Masked Isolation) or MF.sup.3 R (Modified Fully Framed Fully Recessed), uses a silicon etch and sidewall nitride layer to suppress the lateral encroachment of the field oxide. That is, after the patterned first nitride layer defines the active device regions, a silicon etch is then performed where the field oxide regions will be, and a sidewall nitride is deposited (over a pad oxide) on the sidewalls of this etched recess, to avoid encroachment of the field oxide into the active device regions. This general approach has the advantage of being easily integrated in standard MOS process flows, requires no additional photomasking steps, and can reduce moat encroachment to nearly zero.
However, this process has not generally been adopted in production use, since it still has several major shortcomings. In particular, the joint between the first nitride and second nitride, i.e. between the nitride which defines the moat regions and the nitride which covers the sidewalls of the moat regions, will sometimes fail, leading to a localized bird's-beak. This degrades reliability unacceptably for a production process.
Thus it is an object of the present invention to provide a high-yield isolation method which does not provide large moat encroachment.
It is a further object of the present invention to provide an isolation technology which does not generate substantial moat encroachment, and which does not degrade yield through risk of substantial bird's-beaking.
It is a further object of the present invention to provide a sidewall-nitride silicon-oxidation isolation technology which is highly reliable.
It is a further object of the present invention to provide a sidewall-nitride silicon-oxidation isolation technology which does not degrade yield through risk of localized bird's-beaking.
The present invention provides these and other objects advantageously, by providing a process wherein the stress-relief oxide underneath the first nitride is undercut by an isotropic oxide etch before the second nitride is deposited, so that conformal deposition of the second nitride fills in this undercut underneath the first nitride. Thus, the nitride-nitride joint is reliably tight with increased overlay area, avoiding localized bird's-beaking.
A further embodiment of the present invention performs the original moat patterning not on a nitride/oxide stack, as is conventional, but on oxide/nitride/oxide stack. Thus, then the second nitride is conformally deposited, the stack over the moat regions is an oxide/nitride/oxide/nitride stack. When the second nitride is removed, the full thickness of the first nitride remains in place over the moat regions. Preferably the second oxide is striped before field oxidation, so that there is no uncertainty as to the actual remaining thickness of the hardmask over the moat layers at the time of the channel stop implant. A further advantage of this additional oxide layer is that a heavier dose and energy can be used for the channel stop, without significant penetration through the hard mask.
To achieve these and other objects and advantages, the present invention provides:
A method for fabrication of integrated circuits, comprising the steps of:
providing a monocrystalline silicon substrate;
covering predetermined postions of said substrate with a first patterned composite layer, comprising a first pad layer and a first silicon nitride layer over said first pad layer;
anisotropically etching a recess in said substrate where not covered by said first patterned composite layer;
etching said pad layer to form a cavity under portions of the periphery of said first nitride layer;
conformally depositing a sidewall masking layer to cover sidewalls of said recess and substantially fill said cavity;
anisotropically etching said sidewall masking layer to substantially clear the bottom of said recess;
oxidizing exposed portions of silicon to form isolation oxide in said recess;
removing said first composite layer; and
forming desired active devices in portions of said substrate formerly covered by said first composite layer.